The present invention relates to capacitors and methods of manufacturing the same. More particularly, the present invention relates to integrated circuit (semiconductor) device capacitors contacting an underlying metal plug and methods of manufacturing the same.
As the integration density of integrated circuit (semiconductor) devices has increased, the area occupied by a semiconductor device within a chip has generally decreased. Capacitors for storing information in dynamic random access memory (DRAM) devices are typically required to occupy smaller areas while maintaining the same or larger capacitance as conventional capacitors. Conventionally, to increase the capacitance of such a capacitor, a concave or cylindrical lower electrode may be manufactured and a high-k dielectric layer, such as a TaO layer, may be used. When a high-k dielectric layer is used, a lower electrode may be formed of a material having a high work function, such as ruthenium (Ru) and/or platinum (Pt) to reduce leakage current between the lower electrode and the dielectric layer.
For a concave lower electrode, only the inward walls of a concave are generally used to provide capacitance. As a result, when a distance between the inward walls of the concave becomes narrower with a reduction in a device design rule, depositing a dielectric layer typically becomes more difficult. As a result, the concave lower electrode may be inadequate for highly integrated memory devices.
Although a cylindrical lower electrode may advantageously provide capacitance not only with the inward walls but also with the outward walls thereof, depositing a dielectric layer in such a structure may still be difficult with a reduction in an associated design rule. The cylindrical structure may also be unstable.
As a result of these limitations, a stack-type lower electrode may be used as will be described with reference to FIG. 1. As shown in FIG. 1, an interlayer dielectric (ILD) 15 is formed on an integrated circuit (semiconductor) substrate 10 where, for example, a metal oxide semiconductor (MOS) transistor is formed. A plug 20 is formed in the ILD 15 so as to electrically contact one of the junctions of the MOS transistor, for example, a source region of the transistor. The plug may be formed of TiN, which will generally not react with a subsequently formed noble metal lower electrode.
A stack-type lower electrode 25 is formed contacting the TiN plug 20. The lower electrode 25 may be formed of a noble metal such as Ruthenium (Ru). The lower electrode 25 may be formed using chemical vapor deposition (CVD) by supplying a Ru source and an O2 reactant gas. Subsequently, an electrode thermal treatment (or a preprocessing) may be carried out, for example, at a temperature of about 600° to limit or prevent transformation of the lower electrode 25.
As shown in FIG. 1, a dielectric layer, for example, a TaO layer 30, is deposited on the surface of the lower electrode over the ILD 15. The TaO layer 30 can be deposited using CVD by supplying a Ta source and an O2 reactant source. The TaO layer 30 may be deposited in an O2 atmosphere, which may improve dielectric characteristics thereof. The TaO layer may be thermally treated to improve its dielectric constant. An upper electrode 35 is formed on the TaO layer to complete a capacitor 40.
A conventional capacitor, such as illustrated in FIG. 1, generally has various limitations. The formation of the Ru lower electrode using CVD generally needs O2 and the deposition of the TaO layer 30 also generally requires a large amount of O2. Although it is possible to manufacture a lower electrode using physical vapor deposition (PVD), which generally does not require O2, highly integrated memory devices are generally formed using CVD because the PVD process may degrade step coverage characteristics. Where the lower electrode 25 is formed using CVD, a large amount of O2 is typically solid-dissolved in the lower electrode 25 and the TaO layer 30 and then diffuses to the outside, especially, toward the TiN plug 20. As a result, the surface of the TiN plug 20 may be oxidized and a TiO2 layer 50 may be formed at an interface between the Ru lower electrode 25 and the TiN plug 20. Due to the unwanted TiO2 layer, lifting may occur between the lower electrode 25 and the TiN plug 20 and contact resistance may increase, which may result in failures.
FIG. 2 is a graph of measurement results showing contact resistance of the TiN plug 20 before and after the TaO layer is thermally treated. As shown in FIG. 2, before the thermal treatment, contact resistance between the lower electrode 25 and the TiN plug 20 is about 102 to 104 ohms/number of contacts (Ω/cnt, where cnt is contact area)(which typically depends on the diameter of the contact), which is relatively low. However, as the thermal treatment was provided, the contact resistance is significantly increased to be about 109 Ω/cnt. The thermal treatment may be, for example, a preprocessing of the lower electrode performed before deposition of a dielectric layer.
Furthermore, when a stack-type lower electrode is formed of Ru, O2 contained in the Ru layer generally diffuses into the surface of the electrode as well as the TiN plug 20 while the TaO layer 30 is thermally treated and during other subsequent thermal treatments. As a result, the surface of the lower electrode may suffer agglomeration, which may adversely transform the lower electrode.